Integrated circuit design systems implement processes that often include generating a circuit schematic of an integrated circuit being designed, performing a pre-layout simulation on the circuit schematic to simulate a performance of the integrated circuit, generating a layout of the integrated circuit, and performing a post-layout simulation on the layout of the integrated circuit. Prior art techniques for the pre-layout and post-layout simulation are commonly referred to as dynamic timing analysis or static timing analysis (STA). Each way has its drawbacks and there is a need for a novel solution in this field.